T.P. Ma
Raymond John Wean Professor
Dept. of Electrical Engineering
Yale University
New Haven, CT 06520-8284
Phone: 203-432-4211
Fax: 203-432-7769
Email: t.ma@yale.edu
 

Research
Lab Facilities
StudentLab for course EE421
Cleanroom Facility

Advanced Gate Dielectrics

The continued down scaling of MOS devices has created many challenges and opportunities, among them the formidable requirement for an ultra-thin gate oxide (<1.0 nm in thickness) within a few years. Since the tunneling leakage current for such an ultra-thin oxide will be unacceptable for mainstream ULSI applications, an alternative gate dielectric must be found to sustain the scaling trend. Prof. Ma’s group has studied gate-quality silicon nitride, TiO2, ZrO2, and HfO2 films that exhibit very low leakage current (several orders lower than thermal SiO2) that seems suitable for advanced CMOS technology. This work has attracted the attention of several major semiconductor companies who have conducted joint studies with Prof. Ma.

Additional research remains to be performed to better understand the electronic properties of these advanced dielectric films–hot on the list includes the understanding of channel mobility degradation mechanisms and reliability of high-k gated MOSFETs.

Inelastic Electron Tunneling Spectroscopy (IETS)

IETS is a promising technique to study the microstructures of ultra-thin gate dielectrics where electron tunneling currents are non-negligible. It utilizes tunneling electrons to probe vibrational modes and electronic excitations involving phonons, defects, and impurities in the gate dielectric as well as near its interfaces on both sides. Extensive IETS spectra obtained on ultra-thin (1.5-1.8nm) SiO2/Si exhibit clearly resolvable Si phonons of various modes and Si-O bonding vibration modes, plus structures attributable to impurities such as Si-F and Si-H bonds. IETS measurements on ultra-thin silicon nitride also revealed expected Si phonons and Si-N bonding vibrations. Recent IETS results on high-k dielectrics, such as HfO2 and HfAlO, exhibit many features that may be attributed to the bonding vibrations of the high-k oxide and their interfaces. IETS signals for electronic traps have also been identified, and a technique has been developed to obtain the energy level and physical location of a trap from the combined forward and reverse-biased IETS spectrum. The ultimate aim of this project is to develop IETS into a broadly applicable characterization tool for a variety of ultra-thin dielectrics.

Flash EPROM Memory Devices

Flash EPROM memory devices have found many new applications in recent years, and the list is growing rapidly. The flash memory density has been increasing over the years in accordance to the Moore’s Law, largely due to the down scaling of the memory cell dimensions. One serious problem that severely hinders further scaling is the tunnel oxide, which has stayed at greater than or equal to 8 nm for several generations, because of excessive stress-induced leakage current (SILC) for thinner oxide. Prof. Ma’s group has demonstrated that the use of high-quality silicon nitride as the tunnel dielectric should allow scaling to continue till 5 nm of EOT (equivalent oxide thickness), and the scaled flash memory cell should also enjoy much faster programming speed and lower programming power.

In addition to the traditional floating-gate type of flash memory devices, Prof. Ma's group is also working on SONOS technology, because of it's potential for high-density nonvolatile memory technology, with an emphasis on the use of trap-less silicon nitride to replace silicon oxide to drastically improve the programming efficiency and scalability of SONOS technology.

Prof. Ma’s group is currently working with major semiconductor companies to jointly develop this technology into a commercially viable product.

In collaborating with Prof. Charles Ahn’s group, Prof. Ma’s group is also exploring the possibility of complex crystalline oxides for nonvolatile memory applications.

Ferroelectric Thin Films for Memory Technology

The key property of a ferroelectric material is spontaneous polarization that can be reversed by an applied field. This property is attractive for memory applications. Prof. Ma’s research in this area involves the study of the properties of ferroelectric thin films, as well as the design, simulation, fabrication, and characterization of novel experimental devices based on such ferroelectric thin films.

An invention from this group, based on the idea of a ferroelectric capacitor-less DRAM (FEDRAM) cell, won the 1998 National Collegiate Inventors Award sponsored by the B.F. Goodrich Corporation and the Inventors Hall of Fame. This invention has been granted by the US. Patent Office (# 6067244) in year 2000, and is the basis for a current research project to further develop the FEDRAM idea.

MIS Devices Based on SiC, GaN, GaP, SiGe, and InAs

To explore the potential of high-quality gate dielectrics for semiconductors other than Si, Prof. Ma’s group has done some experiments with SiC, GaN, GaP, SiGe, and InAs, and the results all look encouraging.

Among them the most extensive work has been done on SiC, as SiC is one of the most attractive semiconductors for high-temperature, high-power electronics, but, despite extensive research effort for over a decade, high-quality, high-reliability SiC CMOS transistors have remained elusive, due to the lack of a high-quality high-reliability gate dielectric for both n- and p-channel MOSFETs. For several years, Prof. Ma’s group has been investigating the use of a novel siliconoxide/nitride/oxide (ONO) stack as the gate dielectric for SiC and has achieved unmatched gate dielectric reliability at high temperatures (upto 450 ºC). More work is being carried out to understand the interface properties of SiC MIS systems and their effects on transistors' quality and reliability. In addition to SiC, Prof. Ma’s group has been working on another promising wide bandgap semiconductor, GaN, as well as on several other semiconductors, including SiGe, GaP, and InAs, with the goal of achieving a unified framework for high-quality gate dielectric deposition for all these technologically important semiconductors.

More recently, Prof. Ma's group has used the knowledge base that they have accumulated about MIS interfaces to work on passivation of solar cell surfaces.

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