Miscellaneous Contributions
Trusted Computing & Emerging Technologies :
The expertise developed through our Test and Reliability research has recently led to the initiation of three new activities, corroborating the applicability of our methods to contemporary problems and emerging technologies. First, we are investigating the applicability of our machine learning-based test methods in identifying hardware Trojan horses and designing trusted integrated circuits. Second, in collaboration with Prof. Mark Reed, we are experimenting with machine learning methods for characterizing fabricated nanodevices and developing robust nanoscale architectures. Finally, along with Prof. T.P. Ma and Prof. Charles Ahn, we are exploring novel reconfigurable architectures and computing modalities using non-volatile ferroelectric memories.
Other Topics:
In the past, we also found ourselves toying with ideas in computer architecture, test compaction, and design diagnosis, areas that are related to our interests but which do not fall within our main research threads.
With regards to computer architecture, we developed a method for selectively generating and optimizing the frames constructed by the rePLay architecture statically. Since static analysis provides a global view of the interaction between the basic blocks and a bigger aggressive optimization space, we proposed a method to construct the frames using profiling and static analysis. Frame selection and optimization are analyzed in the criteria to produce well-optimized, frequently executed frames with minimum recovery penalty. In addition, hardware support is reduced to only perform mis-speculation recovery. Empirical results show frame-optimized code outperforming baseline code on the SPEC integer benchmarks. Along a different direction, we analyzed the effect of faults in branch predictors, a representative example of speculative processor subsystems, to motivate the necessity for fault tolerance in such subsystems. We then reviewed the design of fault tolerant branch predictors using general fault tolerance technique and we proposed a fault-tolerant implementation that utilizes the FSM structure of the Pattern History Table (PHT) and the set of potential faulty states to predict the branch direction, yet without strictly identifying the correct state. Our solution provides virtually the same prediction accuracy as general fault tolerant techniques, while significantly reducing the incurred hardware overhead.
With regards to test compaction, we demonstrated the formulation of static compaction of independent test sequences as an Integer Program. Solving the Linear Program relaxation of this Integer Program provides a lower bound for the optimal solution, i.e. the minimal set of test sequences. Subsequently, Randomized Rounding of the optimal point of the Linear Program is employed to obtain a solution for the Integer Program. The key advantage of this approach is that it provides a polynomial time approximation algorithm as well as an indication of proximity to the optimal solution and, thus, a measure for evaluating compaction efficiency. As indicated by experimental results, our method is efficiently identifying nearly optimal solutions.
With regards to design diagnosis, we developed a design-for-debug method through hierarchical test paths. Based on debug information inherently attainable from hierarchical test paths, we outlined a diagnosis algorithm that identifies the minimal set of faulty module candidates, under the single faulty module model. We further provided a disambiguation rule to ensure unfailing identification of the single faulty module. Low-cost, design-for-debug techniques were subsequently proposed for establishing the disambiguation rule and for providing a module diagnosis capability.
