Test & Reliability Solutions
for Digital Circuits
While test and reliability solutions for digital circuits are quite mature, the rapidly advancing technology continues to present challenging problems. Our research in this area has focused on two such problems. First, due to the size and complexity of modern designs, test methods can no longer handle them as monolithic entities. Therefore, we are developing hierarchical test approaches that address the problem in a divide-&-conquer manner. Second, current and near-future CMOS circuits exhibit an increased sensitivity to high-energy neutrons, protons, or alpha particles. When such elements strike a sensitive region in a semiconductor, they can generate a Single-Event Transient (SET) pulse, which may be misinterpreted by the circuit as a valid signal and result in an incorrect state and/or output (soft error). To address this problem, we are developing soft error detection and mitigation design methodologies, which aim to increase circuit reliability, while taking account design constraints such as area, performance, and power consumption.
Key Contributions:
1) RT-Level Hierarchical Testability Analysis and Test Generation:
Based on the introduced notion of transparency channels and pertinent composition algebra, we developed a hierarchical Register Transfer Level (RTL) testability analysis method wherein each module is accessed via reachability paths and treated as a stand-alone entity. Unlike earlier work, where transparency is coarsely defined at fixed bitwidths, channels capture transparency in variable bitwidth threads and enable composition of fine-grained paths, identification of bit-level testability bottlenecks, and cost-effective design modifications to support hierarchical test. A prototype tool, TRANSPARENT, (TRANSlation Path Analysis RENdering Test) was developed and transferred to Intel Corp.
2) Optimization Frameworks for Designing Reliable Circuits:
We developed two design-space exploration frameworks which take into account reliability parameters (e.g. error coverage, detection latency) and design constraints (e.g. area / performance overhead, power consumption), in order to evaluate alternative solutions. The first framework employs parity-based CED and uses the entropy of a function in order to explore the trade-off between error coverage and area/power overhead. Parity forest selection is formulated as an Integer Linear Programming (ILP) and is approximated via Randomized Rounding. The second framework employs rewiring, which has been previously used for optimizing area, power consumption, delay, and testability of a circuit, in order to seamlessly integrate soft error mitigation solutions in the exploration of the design space.
Current Activities & Future Plans:
We are currently investigating concurrent error detection and mitigation methods for controllers of modern microprocessors, focusing on identification of architectural invariant properties and characterization of their effectiveness at the register transfer level and the gate level. This research is funded by and carried out in collaboration with Intel Corp., and aims to leverage architectural-level invariance. In addition, we are continuing our research on developing a comprehensive synthesis-for-reliability framework for soft error tolerance.
