Test & Reliability Solutions
for Analog/RF Circuits
Due to both technological and economical factors, analog/RF designs constitute a rapidly increasing fraction of modern integrated circuits. From a technology perspective, silicon manufacturing now enables integration of digital, analog, and even micro-electro-mechanical parts on the same substrate. From an economical standpoint, the electronics market is experiencing an explosion of new applications where analog/RF circuits are essential, especially in wireless communications, real-time control, and multimedia. As the number of mass-manufactured analog/RF integrated circuits increases, we are faced with new challenges, in order to guarantee their feasibility and economic viability. Among them, our research focuses on developing cost-effective manufacturing test solutions to increase their quality, as well as smart observer modules to increase their reliability.
Key Contributions:
1) A Machine Learning Approach to Analog/RF Test:
We introduced a machine learning-based method which utilizes information learned from a small training set of fully tested analog/RF chips, in order to reduce test cost for the rest of the production. The fundamental advantage of our method is that it does not only predict the pass/fail labels of devices based on a set of low-cost measurements, but it also assesses the confidence in this prediction and retests devices for which this confidence is insufficient through traditional specification testing. Thus, this two-tier test approach sustains the high accuracy of specification testing while leveraging the low cost of machine learning-based testing. By varying the desired level of confidence, it also enables exploration of the trade-off between test cost and test accuracy and facilitates the development of cost-effective test plans. The effectiveness of this method has been demonstrated using real test data provided by Intel Corp.
2) Smart Observer Modules for CED in Analog Circuits:
We developed two Smart Observer Modules capable of characterizing the operation of a circuit as erroneous or error-free. The first module is a checker, which examines two analog signals and decides whether their difference remains within a predefined tolerance window. The innovative feature of our checker is that it dynamically adjusts the width of this window as a percentage of the magnitude of the compared signals and, thus, is more accurate. The second module is an estimator, which monitors the inputs and a few internal nodes of a linear analog circuit and generates an estimate of its output. In error-free operation, this estimate converges rapidly to the actual output value, which it follows exactly from then onwards. In the presence of an error, however, the estimate deviates from the circuit output and the error is detected through the use of a checker, such as the one described above.
Current Activities & Future Plans:
The above contributions have stimulated two complementary lines of research currently pursued in our group. First, we have secured funding from NSF for combining the machine learning test approach with the smart observer modules and developing a stand-alone neuromorphic built-in self-test (BIST) solution for analog/RF circuits. This BIST capability constitutes a key step towards self-healing reconfigurable mixed-signal circuits, which we are also interested in developing. Second, we have secured funding by both NSF and SRC to continue investigating statistical methods for correlating RF and DC measurements and, thereby, reducing the cost of test. Promising results along both of these directions have already been demonstrated on production test data from real circuits, provided by IBM and Texas Instruments.
