Publications
(Complete List)
Book Chapter Contribution:
[1]
L. T. Wang, C. E. Stroud, and N. A. Touba (Editors), “System on-Chip Test
Architectures,” Morgan-Kaufman Publishers, 2007 (Y. Makris, section 8.4,
“Circuit-Level Approaches to Soft Error Mitigation,” (invited)) (link)
Journal Papers:
[2]
S. Almukhaizim, F. Shi, E. Love, Y. Makris, “Soft Error Tolerance and Mitigation in
Asynchronous Burst-Mode Machines,” IEEE Transactions on Very Large Scale
Integration Systems (T.VLSI), 2009 (to appear)
[3]
F. Shi, Y. Makris, “Enhancing Simulation Accuracy through Advanced Hazard
Detection in Asynchronous Circuits,” IEEE Transactions on Computers (T.COMP),
vol. 58, no. 3, pp. 394-408, 2009 (pdf)
[4] H-G. D. Stratigopoulos, Y. Makris, “Error Moderation in Low-Cost Machine Learning-
Based Analog/RF Testing,” IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems (T. CAD), vol. 27, no. 2, pp. 339-351, 2008 (pdf)
[5]
S. Almukhaizim, Y. Makris, “A Novel Soft Error Rate (SER) Reduction Methodology
through Addition of Gate-Level Functional Redundancy,” IEEE Transactions on
Reliability (T. REL), vol. 57, no. 1, pp. 23-31, 2008 (pdf)
[6] S. Almukhaizim, Y. Makris, “Concurrent Error Detection Methods for Asynchronous
Burst Mode Machines,” IEEE Transactions on Computers (T. COMP), vol. 56, no. 6,
pp. 785-798, 2007 (pdf)
[7] Y. Makris, A.
Orailoglu, “On the Identification
of Modular Test Requirements for Low
Cost Hierarchical Test Path Construction,” Integration: The VLSI
Journal (JVLSI),
Elsevier, vol. 40, no. 3, pp. 315-325, 2007 (pdf)
[8]
H-G. D. Stratigopoulos, Y. Makris, “An Adaptive
Checker for the Fully Differential
Analog
Code,” IEEE Journal of Solid-State Circuits (JSSC), vol. 41, no. 6,
pp. 1421-1429, 2006 (pdf)
[9] S. Almukhaizim, P. Drineas, Y. Makris, “Entropy-Driven Parity-Tree Selection
for Low-Overhead Concurrent Error Detection in Finite State Machines,”
IEEE
Transactions on Computer-Aided
Design of Integrated
Circuits and Systems
(T.CAD), vol. 25, no. 8, pp. 1547-1554, 2006 (pdf)
[10]
H-G. D. Stratigopoulos, Y. Makris, “Concurrent
Detection of Erroneous Responses
in
Linear Analog Circuits,” IEEE Transactions on Computer-Aided Design
of
Integrated
Circuits and Systems (T.CAD), vol. 25, no. 6, pp. 878-891, 2006 (pdf)
[11] H-G. D. Stratigopoulos, Y. Makris, “Non-Linear
Decision Boundaries for Testing
Analog
Circuits,” IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems (T.CAD), vol. 24, no. 11, pp. 1760-1773, 2005
(pdf)
[12] S. Almukhaizim, P. Drineas, Y. Makris, “Compaction-Based Conucrrent Error
Detection
for Digital Circuits,” Microelectronics Journal (MEJ), Elsevier,
vol. 36,
no. 9, pp. 856-862, 2005 (pdf)
[13] H-G. D. Stratigopoulos, Y. Makris, “An Analog
Checker with Input-Relative
Tolerance for Duplicate Signals,” Journal of Electronic Testing:
Theory &
Applications (JETTA), Kluwer Academic Publishers (now Springer), vol.
20,
no.
5, pp. 479-488, 2004 (pdf)
[14] Y. Makris, I. Bayraktaroglu, A. Orailoglu, “Enhancing
Reliability of RTL
Controller-Datapath
Circuits via Invariant-Based Concurrent Test,” IEEE
Transactions
on Reliability (T. REL), vol. 53, no. 2, pp. 269-278, 2004 (pdf)
[15] P. Drineas, Y.
Makris, “SPaRe: Selective Partial Replication for Concurrent
Fault Detection in FSMs,” IEEE Transactions on Instrumentation and
Measurement (T. I&M), vol. 52, no. 6, pp. 1729-1737, 2003 (pdf)
[16] Y.
Makris, J. Collins, A. Orailoglu, “Fast Hierarchical Test
Path Construction
for Circuits with DFT-Free Controller-Datapath Interface,”
Journal of
Electronic Testing: Theory & Applications (JETTA), Kluwer Academic
Publishers (now Springer), vol. 18, no. 1, pp. 29-42,
2001 (pdf)
[17] Y.
Makris, A. Orailoglu, “RTL Test Justification and Propagation
Analysis for
Modular Designs,” Journal of Electronic Testing:
Theory & Applications
(JETTA), Kluwer Academic Publishers (now Springer),
vol. 13, no. 2, pp.
105-120, 1998 (pdf)
Conference
Papers:
[18] M. Maniatakos, N. Karimi, C. Tirumurti, A. Jas, Y. Makris, “Instruction-Level Impact
vs. Gate-Level Faults in a Modern Microprocessor Controller,” Proceedings of the
IEEE VLSI Test Symposium, 2009 (to appear)
[19] H-G. Stratigopoulos, Y. Makris, “Enrichment of Limited Training Sets in Machine
Learning-Based Analog/RF Test,” Proceedings of the IEEE Design Automation and
Test in Europe Conference (DATE), 2009 (to appear)
[20] N. Karimi, M. Maniatakos, A. Jas, Y. Makris, “On the Correlation between Controller
Faults and Instruction-Level Errors in a Modern Microprocessor,” Proceedings of the
IEEE International Test Conference (ITC), pp. 24.1.1-24.1.10, 2008 (pdf)
[21] M. Maniatakos, N. Karimi, Y. Makris, A. Jas, C. Tirumurti, “Design and Evaluation of
a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern
Microprocessor Controller,” Proceedings of the IEEE International Symposium on
Defect and Fault Tolerance in VLSI Systems (DFTS), pp. 454-462, 2008 (pdf)
[22] S. Almukhaizim, Y. Makris, Y.-S. Yang, A. Veneris, “On the Minimization of Potential
Transient Errors and SER in Logic Circuits using SPFD,” Proceedings of the IEEE
International On-Line Testing Symposium (IOLTS), pp 123-128, 2008 (pdf)
[23] Y. Jin, Y. Makris, “Hardware Trojan Detection using Path Delay Fingerprint,”
Proceedings of the IEEE International Workshop on Hardware Oriented Security
and Trust (HOST), pp 54-60, 2008 (pdf)
[24] N. Kupp, P. Drineas, M. Slamani, Y. Makris, “Confidence Estimation in Non-RF
to RF Correlation-Based Specification Test Compaction,” Proceedings of the IEEE
European Test Symposium (ETS), pp 35-41, 2008 (pdf)
[25] J. Dardig, H-G. Stratigopoulos, E. Stern, M. Reed, Y. Makris, “A Statistical Approach
to Characterizing and Testing Functionalized Nanowires,” Proceedings of the IEEE
VLSI Test Symposium (VTS), pp. 267-274, 2008 (pdf)
[26] S. Almukhaizim, F. Shi, Y. Makris, “Coping with Soft Errors in Asynchronous Burst-
Mode Machines,” Proceedings of the IEEE International Symposium on Asynchronous
Circuits and Systems (ASYNC), pp. 151-160, 2008 (pdf)
[27]
H-G. D. Stratigopoulos, P. Drineas, M. Slamani, Y. Makris, “Non-RF to RF Test
Correlation Using Learning Machines: A Case Study,” Proceedings of the IEEE
VLSI Test Symposium (VTS), pp. 9-14, 2007 (pdf)
[28]
F. Shi, Y. Makris, “Testing Delay Faults in Asynchronous Handshake Circuits,"
Proceedings of the IEEE
International Conference on Computer-Aided Design
(ICCAD), pp. 193-197, 2006 (pdf)
[29]
S. Almukhaizim, Y. Makris, Y.-S. Yang, A. Veneris, “Seamless Integration of SER in
Rewiring Based Design Space Exploration,” Proceedings of the IEEE
International
Test Conference (ITC), pp. 29.3.1-29.3.9, 2006 (pdf)
[30] H-G. D. Stratigopoulos, Y. Makris, “Bridging
the Accuracy of Functional and Machine-
Learning-Based Mixed-Signal Testing,”
Proceedings of the IEEE VLSI Test
Symposium (VTS), pp. 406-411, 2006 (pdf)
[31] G. Gill,
A. Agiwal, M. Singh, F. Shi, Y. Makris, “Low-Overhead
Testing of Delay Faults
in High-Speed Asynchronous Pipelines,” Proceedings
of the IEEE International
Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 46-56, 2006 (pdf)
[32] F. Shi, Y. Makris, “A Transistor-Level Strategy for C^2MOS
MOUSETRAP
Asynchronous Pipelines,” Proceedings of the IEEE International Symposium
on Asynchronous
Circuits and Systems (ASYNC), pp. 57-66, 2006 (pdf)
[33]
S. Almukhaizim, Y. Makris, “Berger-Code-Based Concurrent
Error Detection in
Asynchronous Burst-Mode Machines,” Proceedings of the IEEE
Design Automation
and Test in Europe Conference (DATE), pp. 71-72, 2006 (pdf)
[34] F.
Shi, Y. Makris, S. Nowick, M. Singh, “Test Generation
for Ultra-High-Speed
Asynchronous Pipelines," Proceedings of the IEEE International
Test Conference
(ITC), pp.
39.1 - 39.10, 2005 (pdf)
[35] H-G. D. Stratigopoulos, Y. Makris, “Constructive
Derivation of Analog Specification
Test Criteria,” Proceedings of the IEEE VLSI Test Symposium
(VTS), pp. 395-400,
2005 (pdf)
[36] H-G. D. Stratigopoulos, Y. Makris, “Generating
Decision Regions in Analog
Measurement Spaces,”
Proceedings of the ACM Great Lakes Symposium in VLSI
(GLSVLSI),
pp. 88-91, 2005 (pdf)
[37]
S. Almukhaizim, Y. Makris, “Concurrent Error Detection
in Asynchronous
Burst-Mode Controllers,” Proceedings of the IEEE Design
Automation and
Test in Europe Conference (DATE), pp. 1272-1277, 2005 (pdf)
[38] F. Shi, Y. Makris, “SPIN-PAC: Test Compaction for Speed-Independent
Circuits,” Proceedings of the IEEE Asian South Pacific Design
Automation
Conference (ASP-DAC), pp. 71-74, 2005
(pdf)
[39] F. Shi, Y. Makris, “SPIN-TEST: Automatic Test Pattern Generation
for Speed-
Independent Circuits,” Proceedings of the IEEE International
Conference on
Computer-Aided
Design (ICCAD), pp. 903-908, 2004 (pdf)
[40] F. Shi, Y. Makris, “SPIN-SIM: Logic and Fault Simulation
for Speed- Independent
Circuits,” Proceedings of the IEEE International Test Conference
(ITC), pp.
597-606, 2004 (pdf)
[41] F. Shi,
S. Almukhaizim, P. C. Lin, Y. Makris, “Compiler-Based
Frame
Formation for Static Optimization,” Proceedings of the IEEE International
Conference
on Computer Design (ICCD), pp. 466-471, 2004 (pdf)
[42] F. Shi, Y. Makris, “Fault Simulation and Random Test Generation
for Speed Independent
Circuits,” Proceedings of the ACM Great Lakes Symposium
on VLSI (GLSVLSI), pp. 127-130, 2004 (pdf)
[43] S. Almukhaizim,
P. Drineas, Y. Makris, “Cost-Driven Selection of Parity
Trees,”
Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 319-324,
2004 (pdf)
[44] S. Almukhaizim,
P. Drineas, Y. Makris, “Concurrent Error Detection
for
Combinational and Sequential Logic via Output Compaction,” Proceedings
of the IEEE International Symposium on Quality Electronic Design (ISQED),
pp. 459-464, 2004 (pdf)
[45] S. Almukhaizim,
P. Drineas, Y. Makris, “On Concurrent Error Detection
with
Bounded Latency in FSMs,” Proceedings of the IEEE Design Automation
and
Test in Europe Conference (DATE), pp. 596-601, 2004 (pdf)
[46] K. Rokas, Y. Makris, D. Gizopoulos, “Low-Cost Convolutional
Code Based Concurrent
Error Detection in FSMs,” Proceedings of the IEEE International
Symposium
on Defect and Fault Tolerance in VLSI Systems (DFTS), pp.
563-570,
2003 (pdf)
[47] S. Almukhaizim, Y. Makris, “Fault Tolerant Design of Combinational
and
Sequential Logic based on a Parity Check Code,” Proceedings of the
IEEE International
Symposium on Defect and Fault Tolerance in VLSI Systems
(DFTS),
pp. 344-351, 2003 (pdf)
[48] S. Almukhaizim,
T. Verdel, Y. Makris, “Cost-Effective Graceful
Degradation
in Speculative Processor Subsystems: The Branch Prediction Case,”
Proceedings of the IEEE International Conference on Computer Design
(ICCD), pp. 194-197, 2003 (pdf)
[49] P. Drineas, Y. Makris, “Independent Test Sequence Compaction
through
Integer Programming,” Proceedings of the IEEE International
Conference on
Computer Design (ICCD), pp. 380-386, 2003
(pdf)
[50] H-G. D. Stratigopoulos, Y. Makris, “Concurrent Error Detection in Linear
Analog Circuits Using State Estimation,” Proceedings of the IEEE
International
Test Conference (ITC), pp. 1164-1173, 2003 (pdf)
[51] H-G.
D. Stratigopoulos, Y. Makris, “An Analog Checker
with Input-Relative
Tolerance for Duplicate Signals,” Proceedings of the IEEE On-Line
Test
Symposium (IOLTS), pp. 54-58, 2003 (pdf)
[52] S. Almukhaizim,
P. Drineas, Y. Makris, “On Compaction-Based Concurrent
Error Detection,” Proceedings of the IEEE On-Line Test Symposium
(IOLTS),
pp.
157, 2003 (pdf)
[53] H-G.
D. Stratigopoulos, Y. Makris, “An Analog Checker
with Dynamically
Adjustable Error Threshold for Fully Differential Circuits,” Proceedings
of the
IEEE VLSI Test Symposium (VTS), pp. 209-214, 2003 (pdf)
[54] P. Drineas, Y. Makris, “Concurrent Fault Detection in Random
Combinational
Logic,” Proceedings of the IEEE International Symposium on Quality
Electronic
Design (ISQED), pp. 425-430, 2003 (pdf)
[55] P. Drineas, Y. Makris, “Non-Intrusive Concurrent Error Detection
in FSMs
through State/Output Compaction and Monitoring via Parity Trees,”
Proceedings
of the Design Automation and Test in Europe Conference (DATE), pp. 1164-
1165, 2003 (pdf)
[56] P. Drineas, Y. Makris, “SPaRe: Selective Partial Replication
for Concurrent
Fault Detection in FSMs,” Proceedings of the IEEE International
Conference
on VLSI Design (VLSI), pp. 167-173, 2003 (pdf)
[57] P. Drineas, Y. Makris, “Non-Intrusive Design of Concurrently
Self-Testable
FSMs,” Proceedings of the IEEE Asian Test Symposium (ATS), pp. 33-38,
2002 (pdf)
[58] Y.
Makris, A. Orailoglu, “Test Requirement Analysis for Low
Cost Hierarchical
Test Path Construction,” Proceedings of the IEEE Asian Test Symposium
(ATS),
pp.134-139, 2002 (pdf)
[59] T. Verdel, Y. Makris, “Duplication-Based Concurrent Error
Detection in
Asynchronous Circuits: Shortcomings and Remedies,” Proceedings of
the
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
(DFTS),
pp. 345-353, 2002 (pdf)
[60] Y.
Makris, V. Patel, A. Orailoglu, “Efficient Transparency
Extraction and
Utilization in Hierarchical Test,” Proceedings of the IEEE VLSI
Test Symposium
(VTS), pp. 246-251, 2001 (pdf)
[61] Y.
Makris, J. Collins, A. Orailoglu, “Fast Hierarchical Test
Path Construction
for Controller-Datapath Circuits without DFT,” Proceedings of the
IEEE Asian
Test Symposium (ATS), pp. 185-190, 2000 (pdf)
[62] Y.
Makris, J. Collins, A. Orailoglu, “How to Avoid Random
Walks in Hierarchical
Test Path Identification,” Formal Proceedings of the IEEE European
Test
Workshop (ETW), pp. 163-168, 2000 (pdf)
[63] Y.
Makris, A. Orailoglu, P. Vishakantaiah, “Modular Test Generation
and
Concurrent Transparency-Based Test Translation Using Gate-Level ATPG,”
Proceedings
of the IEEE Custom Integrated Circuits Conference (CICC), pp.
75-78, 2000 (pdf)
[64] Y.
Makris, J. Collins, A. Orailoglu, P. Vishakantaiah, “Transparency-Based
Hierarchical
Test Generation for Modular RTL Designs,” Proceedings of the
IEEE International Symposium of Circuits and Systems (ISCAS), pp. II 689-692,
2000 (pdf)
[65] Y.
Makris, I. Bayraktaroglu, A. Orailoglu, “Invariance-Based
On-Line Test for
RTL Controller-Datapath Circuits,” Proceedings of the IEEE VLSI
Test
Symposium (VTS), pp. 459-464, 2000 (pdf)
[66] Y.
Makris, A. Orailoglu, “A Module Diagnosis and Design-for-Debug
Methodology based on Hierarchical Test Paths,” Proceedings of the
IEEE
International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS),
pp. 339-347, 1999 (pdf)
[67] Y.
Makris, A. Orailoglu, “Property-Based Testability Analysis
for Hierarchical
RTL Designs,” Proceedings of the IEEE International Conference on
Electronics Circuits
and Systems (ICECS), pp. 1089-1092, 1999 (pdf)
[68] Y.
Makris, J. Collins, A. Orailoglu, P. Vishakantaiah, “TRANSPARENT:
A
System for RTL Testability Analysis, DFT Guidance and Hierarchical Test
Generation,” Proceedings of the IEEE Custom Integrated Circuits
Conference
(CICC),
pp. 159-162, 1999 (pdf)
[69] Y.
Makris, A. Orailoglu, “Channel-Based Behavioral Test Synthesis
for
Improved Module Reachability,” Proceedings of the Design Automation
and
Test in Europe Conference (DATE), pp. 283-288, 1999 (pdf)
[70] Y.
Makris, A. Orailoglu, “DFT Guidance Through RTL Test Justification
and Propagation
Analysis,” Proceedings of the IEEE International Test Conference
(ITC),
pp. 668-677, 1998 (pdf)
Papers in Workshops with Informal Proceedings:
[71]
S. Almukhaizim, P. Drineas, Y. Makris, “Roving
Concurrent Error Detection for
Logic Circuits,” Presented at the IEEE North Atlantic Test Workshop,
Essex
Junction, VT, USA, May ’04 (pdf)
[72] S. Almukhaizim, Y. Makris, “Fault Tolerant Design of Random Logic
based on
a Parity Check Code,” Presented at the IEEE European Test Workshop,
Maastricht, Netherlands, May ’03 (pdf)
[73] P. Drineas, Y. Makris, “On the Compaction of Independent Test
Sequences for Sequential
Circuits,” Presented at the IEEE European Test Workshop,
Maastricht, Netherlands, May ’03 (pdf)
[74] Y.
Makris, A. Orailoglu, “Reducing Hierarchical Test Path
Cost via Modular Test
Requirement
Analysis,” Presented at the IEEE European Test Workshop, Corfu,
Greece,
May ’02 (pdf)
[75] P. Drineas, Y. Makris, “Non-Intrusive Design of Concurrently
Self-Testable
FSMs,” Presented at the IEEE North Atlantic Test Workshop, Montauk,
NY, USA,
May ’02 (pdf)
[76] Y.
Makris, A. Orailoglu, “Test Requirement Analysis for Low
Cost Hierarchical
Test Path Construction,” Presented at the IEEE International Workshop
of RTL
Test Generation, Nara, Japan, Nov ’01 (pdf)
[77] Y.
Makris, J. Collins, A. Orailoglu, “How to Avoid Random
Walks in Hierarchical
Test Path Identification,” Presented at the IEEE European Test Workshop,
Cascais, Portugal, May ’00 (pdf)
[78] Y.
Makris, A. Orailoglu, “Exploiting Off-Line Hierarchical
Test Paths in Module
Diagnosis and On-Line Test,” Presented at the IEEE Latin American
Test
Workshop, Rio de Janeiro, Brazil, Feb ’00 (pdf)
[79] Y.
Makris, A. Orailoglu, “Property-Based RTL Test Justification
and
Propagation Analysis,” Presented at the IEEE International
Test Synthesis
Workshop, Santa Barbara, CA, USA, Mar ’98 (pdf)
