Committee

General Chairs

Michael Nicolaidis, TIMA

Yervant Zorian, Virage Logic

Vice General Chair
Rajesh Galivanche, Intel

Lorena Anghel, TIMA

Program Chairs -
Adit Singh, Auburn U.

Sreejit Chakravarty, LSI

Vice Program Chairs

TBD

Finance Chair:

Dimitris Gizopoulos, Pireaus U.

Publicity Chair:

Yiorgos Makris , Yale University

Panels Chair

Subhasish Mitra, Stanford U.

Publications Chair:

Saibal Mukhopadhyay, GaTech

Program Committee

D. Appello, STM

S. Bhunia, Case W. Reserve U.

Y. Cao, Arizona State U.

V. Chandra, ARM

A. Chatterjee, GeorgiaTech

P. Ekakkumanan, IBM

A. Haggag, Freescale

R. Kumar, U. Illinois

P. Li, Texas A&M U.

A. Majumdar, AMD

R. Parekhji, Texas Instruments

I. Polian, U. Freiburg

S.M. Reddy, U. Iowa

S. Sapetnekar, U. Minnesota

N. Seifert, Intel

V. Singh, Indian Inst. of Science

R. Sridhar, SUNY Buffalo

M. Tehranipoor, U. Connecticut

R. Teju, NVIDIA

A. Vassighi, Intel

R. Venkatraman, LSI

X. Vera, Intel

L.C. Wang, UCSB

H.J., Wunderlich, U. Stuttgart

Q. Xu, Chinese U. Hong Kong

S.J. Wen, Cisco

N.E. Zergainoh, TIMA

November 5-6, 2009

Austin, TX, USA

Held in Conjunction with ITC Test Week (ITC 2009)

Call for Papers Advance Program

Objectives

As silicon based CMOS technologies are fast approaching their ultimate limits, reliability is threatened by issues such as process, voltage and temperature variability, accelerated aging and wearout, radiation induced soft-errors and cross talk. In particular, variability of process, voltage and temperature represent a significant threat not only for parametric yield but also for reliability, since they induce timing faults that are extremely difficult to detect during manufacturing testing. It results on increasing ratio of circuits passing fabrication test that are susceptible to manifest failures in the field.

These problems are creating barriers to further technology scaling and are forcing the introduction of new process, design and test solutions aimed at maintaining acceptable levels of reliability.

As elimination of these issues is becoming increasingly difficult, various design techniques are emerging to circumvent them. These techniques may incur area, power, yield or performance penalties. Thus, to enable their adoption by the industry there is need for novel solutions to minimize penalties and provide automation tools.
The goal of this workshop is to create an informal forum to discuss those design, EDA and test innovations enabling chips to maintain acceptable reliability levels at reasonable cost. The workshop is sponsored by the IEEE Computer Society Test Technology Technical Council.

Representative topics include, but are not limited to:

ü Reliability issues in advanced CMOS

ü Variability-aware design

ü Radiation effects in advanced CMOS

ü Design for reliability in advanced CMOS

ü Fault tolerant architectures

ü Variability mitigation

ü Self-calibrating architectures

ü On-line monitoring of circuit parameters

ü Design automation for self-calibrating and fault tolerant architectures

ü Variability insensitive architectures

ü Reliability assessment tools

Submissions To present at the Workshop, authors are invited to submit previously unpublished technical proposals. The proposals may be draft presentations, extended abstracts (500 words), or full papers. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and keywords.  Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address.

Submit a copy of your proposal by PDF, via E-mail to : drvw2009@auburn.edu

Proposals for panel discussions are also invited.

Submissions are due no later than September 20, 2009. Authors will be notified of the disposition of their presentation by October 9, 2009. Authors of accepted presentations must submit the final presentation by October 19, 2008 for inclusion in the Workshop Proceedings, which will be provided to the attendees on a memory stick. Optionally, an extended abstract or paper can also be included in the notes.

General Information

Michael Nicolaidis, TIMA Laboratory	Yervant Zorian, Virage Logic
Tel: +33476575060 Fax: +33 4 76 57 49 81 Email: michael.nicolaidis@imag.fr	Tel: +1 (510) 360-8035 Fax: +1 (510) 360-8078 yervant.zorian@viragelogic.com