Building Bayesian Networks with Analog Subthreshold CMOS Circuits

Samuel B. Luckenbill
sbl23@pantheon.yale.edu
Department of Electrical Engineering
Yale University
15 Prospect Street
New Haven, CT 06511

Abstract:

Bayesian networks are graphical models that map together existing beliefs about the relationships between events and provide a mathematical rule explaining how to change those beliefs in light of new evidence. These networks are useful in computationally demanding decision-making applications such as decoding turbo codes, and translate naturally into analog circuits. This paper explores the process of creating these subthreshold CMOS circuits and testing their efficacy.