This paper presented Bayesian networks and a set of circuits that can be used to solve them. The equations that describe the behavior of various analog subthreshold CMOS circuits, including the equation for a single subthreshold MOS transistor, were derived. Trellis modules for simple boolean logic gates were then presented and explained. With these fundamental circuits, sum-product circuits for specific function-to-variable and variable-to-function nodes were constructed. A small example network was then constructed and analyzed. The results were somewhat inconclusive due to the limitations of the available CAD tools, but an intuitive understanding of the circuits and their behavior led us to believe that they are much faster than their digital counterparts. Finally, several suggestions for future work were given and their importance explained.