This limited study of analog subthreshold circuits brings up more questions than it solves. Each of the following topics deserves study and will have to be examined before these circuits can become commercially viable.
The most alarming phenomenon observed in this study was that of a single current mirror exhibiting oscillation. If this behavior is real and not an artifact of a poor subthreshold transistor model, the future of this technology seems bleak. The problem seems to arise when the gate capacitance is equal to the capacitance from the drain to the gate and the transistor is able to oscillate. Solving this problem is a matter of figuring out whether or not the capacitance model of the BSIM3 transistor model is accurate in the subthreshold range, which it may or may not be.
If BSIM3 is accurate and the simulations can be trusted, a possible solution is to minimize the capacitances by avoiding large transistor geometries in current mirrors. If the simulations are not accurate, a new model must be created that can correctly simulate the subthreshold region of a MOS transistor. BSIM4 or other commercial simulators may do this already, but BSIM4 requires parameter files that are not often available from chip manufacturers.
The assumption that the behavior of subthreshold analog MOS transistors is almost identical to bipolar transistors is generally traced back to Carver Mead and his book, ``Analog VLSI and Neural Systems." This book presented many sample implementations of neural networks, all based on subthreshold CMOS VLSI. Many of these circuits were not actually fabricated and tested, and so their validity should be questioned. The stability of Mead's circuits is not addressed in his book and is also in question. Before work on probability propagation circuits continues, Mead's circuits should be thoroughly examined and tested. Circuits that are not stable should be fixed, and the methods used to diagnose and fix those circuits should be published.
If we find that the subthreshold CMOS circuits that perform the sum-product algorithm are indeed stable, their performance needs to be carefully measured. As mentioned before, analog circuits are most useful for computations where speed is more important than accuracy. At this point we can only assume that the subthreshold CMOS circuits are fast. A more through project would examine the nature of the transient analysis that SPICE performs, and compare it against the real behavior of a subthreshold circuit. Some modification of SPICE or the BSIM models may make this type of simulation more accurate and would be an important step toward commercially feasible analog subthreshold devices.
Although the definition of a Bayesian network specifies that it be acyclic, some problems such as decoding Turbo codes require solving networks with cycles in them. The simple solution to this problem is to choose a message passing algorithm and flatten the networks so that no cycles exist in the circuit. This is not the most ideal solution, however. We would like to be able to have large cycles without duplicating a large amount of logic. It is also likely that a circular network that is convergent for all inputs will be faster than a flat one because of its smaller size.
Stability problems are difficult to solve, especially with inaccurate models. The first step toward solving this problem is to fully understand the instability seen in the current mirror and fix the transistor models if necessary. With a good understanding of the current mirror, the stability of specific networks with specific inputs could be verified. The eventual goal should be to design networks that are stable regardless of the input and the number of cycles. Additional circuitry may need to be added to the existing networks that allows the networks to converge in all cases. The design of these supplementary building blocks and their application to cyclic networks is a substantial problem.
After tackling all of the underlying problems, we can address the lack of good CAD tools for building subthreshold circuits that implement Bayesian networks. Appendix A describes the tool built for this project, its structure, function, and shortcomings. In short, the tool can parse an XML description of a Bayesian network, solve that network in software, and export a partial SPICE netlist that describes a sum-product circuit that implements that network. This is a good start, but needs many improvements.
An important addition to the CAD tool would be an optimization step wherein the naive transistor sizing in the scaling current mirrors is adjusted for accuracy. To implement this, a more thorough study of the behavior of the current mirrors would be necessary. We saw in figure 16 that the accuracy of the current mirror decreased exponentially as the amount of scaling increased. It may be possible to simply increase the widths of the transistors in the train to compensate for this effect.
Currently, the tool blindly creates networks in the exact structure of the factor graph representation of a Bayesian network. This is rarely optimal, as any function on the edge of a graph as well as the variable it connects to, has one input and one output and does no computation. The only thing that can happen in these nodes is degradation of the signal, and there is some propagation delay through them that degrades performance. Their detection and elimination throughout the circuit would be a valuable optimization.
Another type of optimization involves looking for any two circuits that compute the same value and changing them into a single circuit. This may or may not be valuable because making a copy of a current requires two current mirrors and computing a value may require only two transistors. The tool would have to detect when this type of optimization would be valuable and when it would not. Some weight may also be given to ease of layout on a chip and maintaining a logical network structure.
As mentioned before, circular networks may be necessary to solve certain problems. Without further study of their behavior in terms of convergence and stability, it is difficult to say whether or not time should be spent on modifying the CAD tool to support them. At this point it makes more sense give the tool the functionality to flatten the cyclic network, but choosing the correct routing algorithm for this is a difficult and requires some knowledge of the problem to be solved with that network. At the very least, the tool should prompt the user for an appropriate routing.
As a last step, the application of analog subthreshold CMOS to some real-world problems and thorough testing of those circuits will move the technology closer to commercial viability. Turbo codes may not be the best choice, as they are not yet used in real-world applications. A nice project might replace the decoding logic in a DSL or cable modem with sum-product circuits, which, if functional, would demonstrate the efficacy of the technology.