Chun-Chen Yeh Research Assistant, PhD student Becton Center # 317 Department of Electrical Engineering Yale University New Haven, CT 06520 Lab phone: 203-432-4209 Email: chun-chen.yeh@yale.edu
2004~	Electrical Engineering, Yale University
1999	M.S., National Tsing-Hua University, Taiwan
1997	B.S., National Tsing-Hua University, Taiwan

Research Summary

My research focuses on the high-k material electrical characterization and modeling for SONOS memory application. Through barrier engineering, advanced tunneling dielectrics are developed, making them ideal candidates for low-voltage embedded flash application. Conduction mechanisms of high-k tunneling dielectrics are studied, and charge trapping, as well as interface properties is characterized using C-V, I-V and charge pumping technique.

Before joining Yale, I spent five years in Taiwan Semiconductor Manufacturing Company as a product engineer, identifying and solving the performance and yield problems of advanced VLSI technologies.

Patent & Publications

1. C. C. Yeh, Y. X. Liu, X. W. Wang, T. P. Ma, Novel Dielectric Stack for Low-Power Embedded Flash Memory Application, CMOC Symposium, Storrs, CT, 2006.

2. C. C. Yeh, Y. X. Liu, X. W. Wang, T. P. Ma, All silicon nitride SONOS-type non-volatile memory device, received Best Student Paper Award at Semiconductor Interface Specialists Conference, Arlington, VA, 2005.

3. C. C. Yeh, T. P. Ma, All silicon nitride SONOS-type non-volatile memory device, filed for U.S. patent 2005.