My research interests focus on testable and reliable design of integrated electronic circuits. 

Testability: 
I develop CAD tools to facilitate the functional and structural examination of integrated circuits and to ensure their quality after manufacturing by detecting permanent faults and defects. 

Reliability: 
I develop design methods that monitor a circuit during its normal operation in the field and report any deviation from the expected functionality due to transient or wear-&-tear errors.

 

My work spans both the digital and the analog domain and addresses synchronous and asynchronous (clock-less) circuits.

Digital domain:
I developed a hierarchical Register Transfer Level (RTL) testability analysis methodology based on the concept of modular transparency. Testability bottlenecks identified by this method have been successfully used to guide DFT modifications and Synthesis-For-Test (SFT) method. 

I devised two hierarchical test generation methods, at the Gate-Level and at the Register Transfer Level. These solutions are incorporated in a prototype tool named TRANSPARENT (TRANSlation Path Analysis RENdering Test), that was transferred to Intel Corp. My contributions also include solutions for test compaction and design of fault tolerant speculative modules. I am currently developing Concurrent Error Detection methods for random combinational and sequential logic, as well as finite state machines. 

Analog domain:
My main focus is the design of methods for unified production and field test. I have developed analog checkers for verifying equivalence of duplicate signals and of fully differential signals. I have also devised a state estimation method for performing concurrent error detection in linear analog circuits. I am currently developing smart classifiers based on artificial neural networks that are trained to distinguish faulty and non-faulty circuit populations based on a minimal number of measurements.

Asynchronous domain:
I have developed several CAD tools for logic simulation, fault simulation, test generation, and test compaction for the class of Speed-Independent circuits. I am currently developing similar methods for other classes of asynchronous circuits. 

Selected Publications

"SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits,"  F. Shi and Y. Makris, in Proceedings of the IEEE International Test Conference (ITC), (to appear in 2004).

"Enhancing Reliability of RTL Controller-Datapath Circuits via Invariant-Based Concurrent Test," Y. Makris, I. Bayraktaroğlu, and A. Orailoğlu, IEEE Transactions on Reliability (T. REL), (to appear June 2004).

"Cost-Driven Selection of Parity Trees," S. Almukhaizim, P. Drineas, Y. Makris,  Proceedings of the IEEE VLSI Test Symposium (VTS), (to appear in 2004).

"On Concurrent Error Detection with Bounded Latency in FSMs," S. Almukhaizim, P. Drineas, Y. Makris, Proceedings of the IEEE Design Automation and Test in Europe Conference, 596-601 (2004).