High performance computer design; microarchitecture for high performance superscalar processors, instruction fetch, trace caches, fill unit design, dynamic instruction optimization.

Selected Publications

"Evaluation of Design Options for the Trace Cache Fetch Mechanism," S.J. Patel, D. H. Friendly, and Y.N. Patt, IEEE Transactions on Computers, 48(2), February (1999).

"Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors," D.H. Friendly, S.J. Patel, and Y.N. Patt, Proceedings of the 31st ACM/IEEE International Symposium on Microarchitecture, Dallas, TX, December (1998).

"Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism," D.H. Friendly, S.J. Patel, and Y.N. Patt, Proceedings of the 30th ACM/IEEE International Symposium on Research,  Triangle Park, North Carolina, November (1997).

"One Billion Transistors, One Uniprocessor, One Chip," Y.N. Patt, S.J. Patel, M. Evers, D.H. Friendly, and J. Stark," IEEE Computer, 30(9), 51(1997).