EE325b
Spring 2002

Class Meeting Topics:

1/16 – intro lecture as per writeup

1/18 – (no lecture, because of MLK holiday switch)

1/23 – diode models, ideal, fixed drop, small signal resistance. Then introduced "equilibrium" thinking to analyze some diode problems from S&S ch.3

1/25 – more diode problems, e.g. S&S P3.111, analyzed by equilibrium principle. Also introduced peak follower, and voltage multiplier (charge pump, as used in flash memory, and Cockroft-Walton multiplier)

1/30 – the small signal model of the diode, exemplified by a diode attenuator. Discussion of the inevitabe interaction between ‘control’ and ‘controlled’ in a two-terminal device. Beginning of use of symmetry to avoid this interaction.

2/1 – full exploration of symmetry in the diode attenuator, different two diode models, use of transformers or differential amplifiers to regain a single-ended output, culminating in the four diode bridge model which best exemplifies IC technology (i.e. no coupling capacitors, fewest resistors).

2/6 – start on transistor (BJT), essential advantages of active components, start of small signal equivalent circuits, start of biasing considerations.

2/8 – further development of themes of biasing and temperature sensitivity, small signal models (pi and T models), beginning of impedance transforming properties of transistor stages.

2/13 – different major configurations (common-emitter, common collector, common base), input & output properties of each. Beginning of biasing C.E. stage with diode-connected other transistor. Results in simple current mirror.

2/15 – another try at biasing the C.E. amplifier by introducing compensating diode(-connected transistor) junction into the emitter branch. This time leads to differential amplifier.

2/20 – properties of differential amplifier, differential and common mode gains, performance requirements for e.g. EKG amplifier.

2/22 – advantages of differential pair with active load, further elaboration of current mirrors, C.E. collector output resistance with added resistor in emitter.

2/27 – Power meter circuit using differential amplifier as transconductance multiplier.

3/1 – Finished some points of power meter (temperature compensation of transconductance, power supply for differential pair); introduced Gilbert gain cell ideas and derived basic gain cell.

3/6 – finished Gilbert gain cell methodology, with examples of multiplier/divider and vector magnitude circuits. Started on overall op amp configuration, the three stages of an op amp circuit (diff. input, gain, emitter-follower output) and their desiderata.

3/8 – more detailed transit through the overall op amp configuration, using the LM324 as example. Explained major design choices, e.g. the Darlington input pair and its transconductance, buffering the gain stage input, the output stage and its current protection.

Spring Break

3/27 – MOS transistor characteristics, bias considerations, linear (triode) vs. saturation regimes.

3/29 – Traversal of MOS amplifier configuration (common-source, common-drain and common-gate) with analogies to BJT equivalents. Comments on input and output impedances, transconductances generally an ordr of magnitude lower than BJT for same bias.

4/3 – "By request" class, announced in advance by email: any circuit question from students. Spent time on rf oscillator circuits, AM and FM radio frequencies, linked it to capacitive and inductive sensing opportunities.

4/5 – The MOSFET as (a nearly ideal) switch in transmission gate form, with implications for audio and signal switching (A/D multiplexer), D/A conversion (R-2R ladder).

4/10 – Combining MOS and BJT configurations: discussion of the CA3130 BiCMOS op amp, its single-supply configuration (current sources, MOS input differential pair, BJT gain stage with A=6000 in a single stage, CMOS inverter output stage. Using its datasheet as typical of op amps, went over the principal specs.

4/12 – Op amp configurations, reverting to the "ideal" op amp. Basic (non)inverting configurations, including single supply operation, idea of constant current environment in feedback path led to biasing a diode that way and to the logarithmic amplifier, idealized half-wave rectifier.

4/17 – more on op amp configurations: unipolar and bipolar programmable current sources, linearization of opto-coupler as analog isolator, potentiostat.

4/19 – example of an electro-mechanical "summing junction", the force-balance scale. It also exemplifies the close symbiosis called "mechatronics." Discussion of diodes in op amp feedback loops, three different versions of absolute-value circuits. Beginning of discussion of the effects of feedback.

4/24 – Feedback as used to stabilize gain, its effect in input and output impedances; the four cases possible when sensing voltage (shunt) or current (series) at the op amp output, and combining voltages (series) or currents (shunt) at the op amp input.

4/26 – An attempt to integrate various understandings about circuit behavior and feedback: taking the "poor man’s power op amp" circuit of Horowitz & Hill Fig. 4.72 as topic, reviewed open loop gain calculations, nonlinearities, possible improvement (e.g. addition of current mirror as input stage collector load), effects of output loading.

4/29 – Miller effect as main frequency limitation in classical common emitter (common source) amplifiers, its deliberate use for dominant pole frequency compensation in op amps, its avoidance in wide-band amplifier via the cascode configuration.

5/1 – Further frequency response issues, open-circuit time constants as way of determining upper 3-db point, look at example op amps schematics to see how implemented.

5/3 - Misc. review of earlier topics, comments on last assignment and take-home final.