• Due Monday May 9th, 5:00pm. Slip under office door if I'm not there. You can also fax to 203-458-3803 or email me electronic formats like .pdf or .doc files. If you fax me or email me scans, be certain to give me a way to reach you in case the fax or scan isn't fully readable (pencil is very vulnerable, pen can be also). Be sure to use good scanning resolution. And in any case, PLEASE use your high-resolution handwriting mode.

• This time you are expected to work these problems ALONE. I will be sensitive to "coincidences" of solutions. You can use any reference materials, books, handouts, databases, notes, though I expect you to cite any references you use. Ask me clarifying questions by email––as usual I'll answer to the class list. Show all your work, to improve the possibility of partial credit.

(1) (25%) Senturia & Wedlock P8.7 (p.224)

(2) Senturia & Wedlock E11.9 (p.337).

(a) (15%) Find I_C1 and I_C2 as stated in the problem .

(b) (20%) Find the incremental voltage gain v_o/v_s. S&W actually ask you to do this more formally as E11.10, but I'd like you to use the simple r_e formalism advocated by me and Horowitz & Hill chapt. 2 (which I handed out).

(3) Let us suppose the University of Ulan Bator in Mongolia, not having been the site of many international conferences, has operated in ways somewhat detached from mainstream electrical engineering, with some unusual research directions. One being the field of ternary logic.

In ternary logic there are "trits" instead of bits, three logical values, "-1", "0", "+1" that could be represented by -5V, 0V, and +5V respectively. The representation of a given ternary number is still a polynomial as in binary, but now with trit weights of 1,3,9,27, etc., the powers of 3. In this problem we will not consider ternary logic circuits as such, but aspects of ternary data conversion. So a digital-to-analog converter (DAC) becomes a ternary-to-analog converter (TAC).

Senturia & Wedlock Fig. P16.12b is a 3-bit DAC based on the R-2R ladder. I gave you a more balanced version in the class discussion, where I inserted another 2R resistor just ahead of the op amp summing junction, mirroring the 2R to ground at the far end. It makes the analysis a lot cleaner. Using this symmetrical version as your starting point, you are to convert it into a 3-trit TAC by finding appropriate resistor ratios. Let's break it into steps:

(a) (20%) The ladder now no longer uses resistors in the 2:1 ratio. You'll have to decide on the ratio for a TAC, best done by just considering the R-2R ladder by itself and how it divides currents and voltages successively by two. An additional resistor at each end, called a "termination resistor" makes up for the finite length. In the R-2R ladder the termination resistor value is 2R, the same as one of the ladder resistors. For ladders of other division ratios, like the 3:1 needed here, the termination resistor is not the same as one of the ladder resistors. Determine the 3:1 ladder resistor ratios for your 3-trit TAC, including termination resistors.

(b) (20%) Now put an op amp at one end, with the op amp summing junction becoming the "ground" for one of the termination resistors. I'll let you pick the feedback resistor value (in units of R). The inputs to the vertical ladder resistors become v_A, v_B and v_C as before, which now assume ternary values of -V₀ , 0 and +V₀ . MOS switches would again be used, but are not part of this problem (see below). Show that the op amp output will be an analog voltage proportional to a three-trit ternary number.

As a fallback, at a loss of half the (a)+(b) credit, you could use the weighted resistor scheme of Fig.P16.12a. It'll still be a 3-trit TAC, but with the disadvantages we discussed in class. What was at least one of those disadvantages (apart from less credit :-)?

Extra Credit Problem: (20%) Just as we discussed for the binary case, the switching of -V₀, 0 and V₀ at each v_A, v_B and v_C input will require a single-pole three-position MOS switch. As Horowitz and Hill explain, such switches are made of individual single-pole single-throw sections, each activated by a binary logic input, because, after all the state of a switch is binary.

You'll recall that in logic circuits logical values are represented by distinguishable ranges of voltages. Assume the ternary logic values are represented by ranges of voltages as follows (all the "<" should really be "equal or greater" but I can't get a reliable html-compatible symbol for that):

Assume the MOS switches are controlled by logic voltages as follows:

Translate, in whatever way you chose, a ternary "trit" input into three binary outputs that would control MOS switches so as to select -V₀, 0 and V₀ at one of your ladder inputs. (You'll need to use "comparators", see S&W pp. 107-109, with Fig. 15.3 being particularly suggestive. You do have to figure out how to make the comparator outputs consistent with the logic inputs that operate the switches.)